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CY62187EV30 mobl ? 64-mbit (4 m 16) static ram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-48998 rev. *f revised june 14, 2011 64-mbit (4 m 16) static ram features very high speed ? 55 ns wide voltage range ? 2.2 v to 3.7 v ultra low standby power ? typical standby current: 8 a ? maximum standby current: 48 a ultra low active power ? typical active current: 7.5 ma at f = 1 mhz easy memory expansion with ce 1 , ce 2, and oe features automatic power down when deselected cmos for optimum speed and power available in pb-free 48-ball fbga package functional description the CY62187EV30 is a high performance cmos static ram organized as 4 m words by 16-bits. this device features advanced circuit design to provide ultra low active current. it is ideal for providing more battery life ? (mobl ? ) in portable applications such as cellular telephones. the device also has an automatic power down feature that significantly reduces power consumption by 99 percent when addresses are not toggling. the device can also be put into standby mode when deselected (ce 1 high or ce 2 low or both bhe and ble are high). the input and output pins (i/o 0 through i/o 15 ) are placed in a high impedance state when: deselected (ce 1 high or ce 2 low), outputs are disabled (oe high), both byte high enable and byte low enable are disabled (bhe , ble high), or during a write operation (ce 1 low, ce 2 high and we low). to write to the device, take chip enables (ce 1 low and ce 2 high) and write enable (we ) input low. if byte low enable (ble ) is low, then data from i/o pins (i/o 0 through i/o 7 ), is written into the location spec ified on the address pins (a 0 through a 21 ). if byte high enable (bhe ) is low, then data from i/o pins (i/o 8 through i/o 15 ) is written into the location specified on the address pins (a 0 through a 21 ). to read from the device, take chip enables (ce 1 low and ce 2 high) and output enable (oe ) low while forcing the write enable (we ) high. if byte low enable (ble ) is low, then data from the memory location specified by the address pins appear on i/o 0 to i/o 7 . if byte high enable (bhe ) is low, then data from memory appears on i/o 8 to i/o 15 . see the truth table on page 9 for a complete description of read and write modes. [+] feedback
CY62187EV30 mobl ? document number: 001-48998 rev. *f page 2 of 15 4096k 16 ram array i/o 0 ?i/o 7 row decoder a 8 a 7 a 6 a 5 a 2 column decoder a 11 a 12 a 13 a 14 a 15 sense amps data-in drivers oe a 4 a 3 i/o 8 ?i/o 15 we ble bhe a 16 a 0 a 1 a 17 a 9 a 18 a 10 power down circuit ce 2 ce 1 a 20 a 19 a 21 logic block diagram [+] feedback
CY62187EV30 mobl ? document number: 001-48998 rev. *f page 3 of 15 contents pin configuration ............................................................. 4 product portfolio .............................................................. 4 maximum ratings............................................................. 5 operating range ............................................................... 5 electrical characteristics ................................................. 5 capacitance ...................................................................... 5 thermal resistance .......................................................... 6 data retention characteristics ....................................... 6 switching characteristics ................................................ 7 switching waveforms ...................................................... 8 truth table ...................................................................... 11 ordering information ...................................................... 12 ordering code definitions ..... .................................... 12 package diagram ............................................................ 13 acronyms ........................................................................ 13 document conventions ................................................. 13 units of measure ....................................................... 13 document history page ................................................. 14 sales, solutions, and legal information ...................... 15 worldwide sales and design s upport ......... .............. 15 products .................................................................... 15 psoc solutions ......................................................... 15 [+] feedback
CY62187EV30 mobl ? document number: 001-48998 rev. *f page 4 of 15 pin configuration figure 1. 48-ball fbga product portfolio product v cc range (v) speed (ns) power dissipation operating i cc (ma) standby i sb2 ( a) f = 1 mhz f = f max min typ [1] max typ [1] max typ [1] max typ [1] max CY62187EV30ll 2.2 3.0 3.7 55 7.5 9 45 55 8 48 we a 11 a 10 a 6 a 0 a 3 ce 1 i/o 10 i/o 8 i/o 9 a 4 a 5 i/o 11 i/o 13 i/o 12 i/o 14 i/o 15 v ss a 9 a 8 oe vss a 7 i/o 0 bhe ce 2 a 17 a 2 a 1 ble v cc i/o 2 i/o 1 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 a 15 a 14 a 13 a 12 a 19 a 18 a 20 3 2 6 5 4 1 d e b a c f g h a 16 vcc a 21 note 1. typical values are included for reference only and are no t guaranteed or tested. typical values are measured at v cc = v cc(typ) , t a = 25 c. [+] feedback
CY62187EV30 mobl ? document number: 001-48998 rev. *f page 5 of 15 maximum ratings exceeding maximum ratings may shorten the useful life of the device. user guidelines are not tested. storage temperature ................ ............... ?65 c to +150 c ambient temperature with power applied ............ ............... ............... ?55 c to +125 c supply voltage to ground potential........................................ ?0.3 v to v cc(max) + 0.3 v dc voltage applied to outputs in high z state [2, 3] .......................?0.3 v to v cc(max) + 0.3 v dc input voltage [2, 3] .................. ?0.3 v to v cc (max) + 0.3 v output current into outputs (low) ............................ 20 ma static discharge voltage......................................... > 2001 v (per mil-std-883, method 3015) latch up current ....... .............. .............. .............. ... > 200 ma operating range device range ambient temperature v cc [4] CY62187EV30ll industrial ?40 c to +85 c 2.2 v to 3.7 v electrical characteristics over the operating range parameter description test conditions 55 ns unit min typ [5] max v oh output high voltage 2.2 v < v cc < 2.7 v i oh = ?0.1 ma 2.0 ? ? v 2.7 v < v cc < 3.7 v i oh = ?1.0 ma 2.4 ? ? v v ol output low voltage 2.2 v < v cc < 2.7 v i ol = 0.1 ma ? ? 0.4 v 2.7 v < v cc < 3.7 v i ol = 2.1 ma ? ? 0.4 v v ih input high voltage 2.2 v < v cc < 2.7 v 1.8 ? v cc + 0.3 v v 2.7 v < v cc < 3.7 v 2.2 ? v cc + 0.3 v v v il input low voltage 2.2 v< v cc < 2.7 v ?0.3 ? 0.6 v 2.7 v < v cc < 3.7 v ?0.3 ? 0.8 [6] v i ix input leakage current gnd < v i < v cc ?1 ? +1 a i oz output leakage current gnd < v o < v cc , output disabled ?1 ? +1 a i cc v cc operating supply current f = f max = 1/t rc v cc = v cc(max) i out = 0 ma cmos levels ?45 55 ma f = 1 mhz ? 7.5 9 ma i sb2 [7] automatic ce power down current?cmos inputs ce 1 > v cc ? 0.2 v or ce 2 < 0.2 v or (bhe and ble ) > v cc ? 0.2 v, v in > v cc ? 0.2 v or v in < 0.2 v, f = 0, v cc = 3.7 v ?8 48 a capacitance parameter [8] description test conditions max unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = v cc(typ) 25 pf c out output capacitance 35 pf notes 2. v il(min) = ?2.0v for pulse durations less than 20 ns. 3. v ih(max) = v cc + 0.75v for pulse durations less than 20 ns. 4. full device ac operation assumes a 100 s ramp time from 0 to v cc (min) and 200 s wait time after v cc stabilization. 5. typical values are included for reference only and are no t guaranteed or tested. typical values are measured at v cc = v cc(typ) , t a = 25 c. 6. under dc conditions the device meets a v il of 0.8 v. however, in dynamic conditions input low voltage applied to the device must not be higher than 0.7 v. 7. chip enables (ce 1 and ce 2 ) and byte enables (bhe and ble ) need to be tied to cmos levels to meet the i sb2 / i ccdr spec. other inputs can be left floating. 8. tested initially and after any design or proce ss changes that may affect these parameters. [+] feedback
CY62187EV30 mobl ? document number: 001-48998 rev. *f page 6 of 15 thermal resistance parameter [9] description test conditions fbga unit ja thermal resistance (junction to ambient) still air, soldered on a 3 4.5 inch, 2-layer printed circuit board 59.06 c/w jc thermal resistance (junction to case) 14.08 c/w figure 2. ac test loads and waveforms table 1. ac test loads parameter 2.5 v 3.3 v unit r1 16667 1103 r2 15385 1554 r th 8000 645 v th 1.20 1.75 v data retention characteristics over the operating range parameter description conditions min typ [10] max unit v dr v cc for data retention 1.5 ? ? v i ccdr [11] data retention current v cc = 1.5 v, ce 1 > v cc ? 0.2 v or ce 2 < 0.2 v or (bhe and ble ) > v cc ? 0.2 v, v in > v cc ? 0.2 v or v in < 0.2 v ??48 a t cdr [9] chip deselect to data retention time 0??ns t r [12] operation recovery time 55 ? ? ns figure 3. data retention waveform [13] v cc v cc output r2 30 pf including jig and scope gnd 90% 10% 90% 10% rise time = 1 v/ns fall time = 1 v/ns output v equivalent to: thevenin equivalent all input pulses r th r1 t cdr v dr > 1.5 v data retention mode t r ce 1 or v cc bhe . ble or v cc(min) v cc(min) ce 2 notes 9. tested initially and after any design or proce ss changes that may affect these parameters. 10. typical values are included for reference only and are no t guaranteed or tested. typical values are measured at v cc = v cc(typ) , t a = 25 c. 11. chip enables (ce 1 and ce 2 ) and byte enables (bhe and ble ) need to be tied to cmos levels to meet the i sb2 / i ccdr spec. other inputs can be left floating. 12. full device operation requires linear v cc ramp from v dr to v cc(min) > 100 s or stable at v cc(min) > 100 s. 13. bhe .ble is the and of both bhe and ble . chip is deselected by either disabling the chip enable signals or by disabling both bhe and ble . [+] feedback
CY62187EV30 mobl ? document number: 001-48998 rev. *f page 7 of 15 switching characteristics over the operating range parameter [14] description 55 ns unit min max read cycle t rc read cycle time 55 ? ns t aa address to data valid ? 55 ns t oha data hold from address change 6 ? ns t ace ce 1 low and ce 2 high to data valid ? 55 ns t doe oe low to data valid ? 25 ns t lzoe oe low to low z [15] 5?ns t hzoe oe high to high z [15, 16] ?20ns t lzce ce 1 low and ce 2 high to low z [15] 10 ? ns t hzce ce 1 high and ce 2 low to high z [15, 16] ?20ns t pu ce 1 low and ce 2 high to power up 0 ? ns t pd ce 1 high and ce 2 low to power down ? 55 ns t dbe ble/bhe low to data valid ? 55 ns t lzbe ble /bhe low to low z [15] 10 ? ns t hzbe ble /bhe high to high z [15, 16] ?20ns write cycle [17] t wc write cycle time 55 ? ns t sce ce 1 low and ce 2 high to write end 45 ? ns t aw address setup to write end 45 ? ns t ha address hold from write end 0 ? ns t sa address setup to write start 0 ? ns t pwe we pulse width 40 ? ns t bw ble /bhe low to write end 45 ? ns t sd data setup to write end 25 ? ns t hd data hold from write end 0 ? ns t hzwe we low to high z [15, 16] ?20ns t lzwe we high to low z [15] 10 ? ns notes 14. test conditions for all parameters other than tri-state paramet ers assume signal transition ti me of 1 v/ns, timing reference levels of v th , input pulse levels of 0 to v cc(typ) , and output loading of the specified i ol /i oh as shown in table 1 on page 6 . 15. at any temperature and voltage condition, t hzce is less than t lzce , t hzbe is less than t lzbe , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any given device. 16. t hzoe , t hzce , t hzbe , and t hzwe transitions are measured when the outputs enter a high impedence state. 17. the internal write time of the memory is defined by the overlap of we , ce 1 = v il , bhe and/or ble = v il , and ce 2 = v ih . all signals must be active to initiate a write and any of these signals can terminate a write by going inactive. the data input setup and hold timing should be referenc ed to the edge of the signal that terminates the write. [+] feedback
CY62187EV30 mobl ? document number: 001-48998 rev. *f page 8 of 15 switching waveforms figure 4. read cycle 1 (address transition controlled) [18, 19] figure 5. read cycle 2 (oe controlled) [19, 20] address data out previous data valid data valid t rc t aa t oha 50% 50% data valid t rc t ace t doe t lzoe t lzce t pu high impedance t hzoe t pd t hzbe t lzbe t hzce t dbe high i cc i sb impedance oe ce 1 address v cc supply current bhe / ble data out ce 2 notes 18. the device is continuously selected. oe , ce 1 = v il , bhe and/or ble = v il , and ce 2 = v ih . 19. we is high for read cycle. 20. address valid prior to or coincident with ce 1 , bhe , ble transition low and ce 2 transition high. [+] feedback
CY62187EV30 mobl ? document number: 001-48998 rev. *f page 9 of 15 figure 6. write cycle 1 (we controlled) [21, 22, 23, 24] figure 7. write cycle 2 (ce 1 or ce 2 controlled) [21, 22, 23, 24] switching waveforms (continued) t hd t sd t pwe t sa t ha t aw t sce t wc t hzoe valid data t bw note 24 address we data i/o oe bhe / ble ce 1 ce 2 t hd t sd t pwe t ha t aw t sce t wc t hzoe valid data note 24 t bw t sa address we data i/o oe bhe / ble ce 1 ce 2 notes 21. the internal write time of the memory is defined by the overlap of we , ce 1 = v il , bhe and/or ble = v il , and ce 2 = v ih . all signals must be active to initiate a write and any of these signals can terminate a write by going inacti ve. the data input setup and hold timing should be referenced to the edge of the signal that terminates the write. 22. data i/o is high impedance if oe = v ih . 23. if ce 1 goes high and ce 2 goes low simultaneously with we = v ih , the output remains in a high impedance state. 24. during this period the i/os are in output state and input signals should not be applied. [+] feedback
CY62187EV30 mobl ? document number: 001-48998 rev. *f page 10 of 15 figure 8. write cycle 3 (we controlled, oe low) [25, 26] figure 9. write cycle 4 (bhe /ble controlled, oe low) [25,26] switching waveforms (continued) valid data t hd t sd t lzwe t pwe t sa t ha t aw t sce t wc t hzwe t bw note 26 address ce 1 ce 2 bhe / ble we data i/o t hd t sd t sa t ha t aw t wc valid data t bw t sce t pwe note 26 address ce 1 ce 2 bhe / ble we data i/o notes 25. if ce 1 goes high and ce 2 goes low simultaneously with we = v ih , the output remains in a high impedance state. 26. during this period the i/os are in output state and input signals should not be applied. [+] feedback
CY62187EV30 mobl ? document number: 001-48998 rev. *f page 11 of 15 truth table ce 1 ce 2 we oe bhe ble inputs outputs mode power hx [27] xxx [27] x [27] high z deselect/power down standby (i sb ) x [27] lxxx [27] x [27] high z deselect/power down standby (i sb ) x [27] x [27] x x h h high z deselect/power down standby (i sb ) l h h l l l data out (i/o 0 ?i/o 15 ) read active (i cc ) l h h l h l high z (i/o 8 ?i/o 15 ); data out (i/o 0 ?i/o 7 ) read active (i cc ) l h h l l h data out (i/o 8 ?i/o 15 ); high z (i/o 0 ?i/o 7 ) read active (i cc ) l h l x l l data in (i/o 0 ?i/o 15 ) write active (i cc ) lhlxhlhigh z (i/o 8 ?i/o 15 ); data in (i/o 0 ?i/o 7 ) write active (i cc ) l h l x l h data in (i/o 8 ?i/o 15 ); high z (i/o 0 ?i/o 7 ) write active (i cc ) l h h h l h high z output disabled active (i cc ) l h h h h l high z output disabled active (i cc ) l h h h l l high z output disabled active (i cc ) note 27. the ?x? (don?t care) state for the chip enables and byte enables in the truth table refer to the logic state (either high or low). intermediate voltage levels on these pins is not permitted. [+] feedback
CY62187EV30 mobl ? document number: 001-48998 rev. *f page 12 of 15 ordering information speed (ns) ordering code package diagram package type operating range 55 CY62187EV30ll-55baxi 001-50044 48-ball fine pitch ball grid array (8 9.5 1.4 mm) pb-free industrial ordering code definitions temperature grade: i = industrial x = pb-free package type: ba = 48-ball fbga speed grade: 55 ns low power voltage range: v30 = 3 v (typical) process technology: e = 90 nm bus width = 16 density = 64-mbit 621 = mobl sram family company id: cy = cypress 621 cy 7 v30 - 55 ba i x ll e 8 [+] feedback
CY62187EV30 mobl ? document number: 001-48998 rev. *f page 13 of 15 acronyms document conventions units of measure package diagram figure 10. 48-ball fbga (8 9.5 1.4 mm) 001-50044 *c acronym description bhe byte high enable ble byte low enable cmos complementary metal oxide semiconductor ce chip enable i/o input/output oe output enable sram static random access memory fbga fine-pitch ball grid array we write enable symbol unit of measure c degree celsius mhz mega hertz a micro amperes ma milli amperes ms milli seconds ns nano seconds ohms % percent pf pico farads vvolts wwatts [+] feedback
CY62187EV30 mobl ? document number: 001-48998 rev. *f page 14 of 15 document history page document title: CY62187EV30 mobl ? 64-mbit (4 m 16) static ram document number: 001-48998 revision ecn orig. of change submission date description of change ** 2595932 vkn/pyrs 10/24/08 new datasheet *a 2644442 vkn/pyrs 01/23/09 updated the package diagram on page 10 *b 2672650 vkn/pyrs 03/12/09 extended the v cc range to 3.7v added 55 ns speed bin and it?s related information changed i cc (typ) from 2.5 ma to 3.5 ma at f = 1 mhz changed i cc (max) from 4 ma to 6 ma at f = 1 mhz for 70 ns speed, changed i cc (typ) form 33 ma to 28 ma at f = f max for 70 ns speed, changed i cc (max) from 40 ma to 45 ma at f = f max for 70 ns speed, changed t pwe from 45 to 50 ns, t sd from 30 to 35 ns modified footnote #6 changed 48-ball fbga package dimensions from 8 x 9.5 x 1.6 mm to 8 x 9.5 x 1.4 mm and updated package diagram on page 10 *c 2737164 vkn/aesa 07/13/09 converted from preliminary to final changed i cc(typ) from 3.5 ma to 4 ma at f = 1 mhz changed i cc(typ) from 35 ma to 45 ma and from 28 ma to 35 ma for the speeds 50 ns and 70 ns respectively at f = f max included v cc range in the test condition of th e ?electrical characteristics? table for the specs v oh , v ol , v ih , v il changed v il(max) from 0.8v to 0.7v for v cc = 2.7v to 3.7v changed c in spec from 20 pf to 25 pf and c out spec from 20 pf to 35 pf included thermal specs for 48-fbga included v cc range for v th spec in the ac test load table changed t lzbe spec from 5 ns to 10 ns added footnote #20 related to chip enable *d 2765892 vkn 09/18/09 removed 70 ns speed for 55 ns speed, at f = 1 mhz, changed i cc (max) spec from 6 ma to 9 ma changed i cc(typ) from 4 ma to 7.5 ma at f = 1 mhz *e 3177000 aju 02/18/2011 updated features (corrected i cc(typ) from 4 ma to 7.5 ma). updated pin configuration (renamed figure 1 as ?48-ball fbga?). updated product portfolio (corrected i cc(typ) from 4 ma to 7.5 ma). updated electrical characteristics (included bhe and ble in i sb2 test conditions to reflect byte power down feature). updated table 1 on page 6 (ac test loads). updated data retention characteristics (included bhe and ble in i ccdr test conditions to reflect byte pow er down feature, corrected t r(min) from t rc to 55 ns). added ordering code definitions . updated package diagram . added acronyms and units of measure . changed all instances of io to i/o. updated in new template. *f 3282088 rame 06/14/2011 updated template as per current cypress standards. removed reference to an1064 sram system guidelines. changed the v il parameter max value to 0.8 v for test condition 2.7 v < v cc < 3.7 v and referenced to footnote # 6. [+] feedback
document number: 001-48998 rev. *f revised june 14, 2011 page 15 of 15 mobl is a registered trademark, and more battery life is a trademark, of cypress semiconductor. all products and company names mentioned in this document may be the trademarks of their respective holders. CY62187EV30 mobl ? ? cypress semiconductor corporation, 2008-2011. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at www.cypress.com/sales. products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 [+] feedback

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